1. Field of the Invention:
The present invention relates to FET circuits, and more particularly metal semiconductor field effect transistors (hereinafter referred to as MESFET) constituting a latch circuit.
2. Description of the Prior Art:
FIG. 1 shows a conventional latch comprising normally-off type MESFETs wherein threshold voltage V.sub.T of the MESFETs is positive. As shown in FIG. 1, the conventional latch has a pair of MESFETs Q.sub.11 and Q.sub.12 which are connected by their common sources to a grounding terminal 12, by their drains through respective resistors R.sub.11 and R.sub.12 to a positive power supply terminal 11, and by their gate electrodes to the drain electrode of the other MESFETs Q.sub.12 and Q.sub.11, respectively. Output terminals 13 and 14 are connected to the drains of the MESFETs Q.sub.11 and Q.sub.12, respectively. In this latch circuit, in order that "H" level and "L" level are issued at the output terminals 13 and 14, respectively, or vice versa, it is necessary that one of the MESFET Q.sub.11 or Q.sub.12 becomes sufficiently on and the other one becomes off or approximately off. Provided that the threshold voltage of the MESFETs of Q.sub.11 and Q.sub.12 are V.sub.T, and the drain-source current of the on-state is I.sub.ON, then for a state of MESFET Q.sub.11 being on a "L" level, voltage V.sub.L becomes EQU V.sub.L =V.sub.DD- I.sub.ON.R.sub.11 (1).
At this time, the voltage V.sub.L is the gate input voltage of the MESFET Q.sub.12, and in order to change the MESFET Q.sub.12 to its off state, the below-mentioned relation is necessary: EQU V.sub.L &lt;V.sub.T ( 2).
In a similar manner, a "H" level voltage V.sub.H at the output terminal 14 is V.sub.DD at this time, or becomes V.sub.DI for a case where the power supply voltage V.sub.DD is higher than Schottky barrier voltage V.sub.DI, and in order to make the MESFET Q.sub.11 on by the V.sub.H voltage at the output terminal 14 the next relation is necessary: EQU V.sub.H &gt;V.sub.T ( 3).
In this circuit if the threshold voltage V.sub.T decreases, the on current I.sub.ON increases, and therefore the "L" level voltage V.sub.L decreases. However, since the threshold voltage V.sub.T has decreased, the above-mentioned relation of inequity (2) holds only for a very limited range of the threshold voltage V.sub.T. When the threshold voltage V.sub.T increases, similarly the relation of the inequity (2) holds only foe a small range of the threshold voltage V.sub.T.
Detailed analysis of the above-mentioned relation has been made by circuit simulation by using a computer, and the simulated results are shown in the graph of FIG. 2, wherein curves V.sub.H and V.sub.L show "H" level voltage and "L" level voltage, respectively, and a line V.sub.C shows voltages of the output terminals 13 and 14 when they become equal instead of being stabilized to "H" level or "L" level by the latching action, i.e., critical voltages to divide the "H" level and "L" level. Differences of this critical voltage and the "H" level or "L" level, namely V.sub.H -V.sub.C, V.sub.C -V.sub.L, are noise margins for latch stabilization.
From observation of the graph of FIG. 2, allowable range of the threshold voltage V.sub.T is about 0.1 to 0.2 volt. Accordingly, deviation .DELTA.V.sub.T of the threshold voltage V.sub.T is allowed only a range of .+-.50 mV. This .+-.50 mV deviation corresponds to very accurate controlling of .+-.40A of a 1000.ANG. thick channel layer when the MESFET is made with a GaAs substrate and carrier concentration of a channel layer is 10.sup.17 cm.sup.-3. Such very accurate controlling of the thickness is practically impossible when such logic circuits are manufactured with a high integration with a high manufacturing yield.
FIG. 3 shows another conventional example of a latch using normally-on type MESFETs having a negative threshold voltage. MESFETs Q.sub.31 and Q.sub.32 correspond to MESFETs Q.sub.11 and Q.sub.12 of FIG. 1 and resistors R.sub.31 and R.sub.32 correspond to resistors R.sub.11 and R.sub.12 of FIG. 1, respectively. In this circuit of FIG. 3 there are two additional MESFETs Q.sub.33 and Q.sub.34 which are connected by their gates to the drains of the MESFETs Q.sub.31 and Q.sub.32, respectively, and by their sources through diodes D.sub.31, D.sub.32 and D.sub.33 to the output terminal 33 and through diodes D.sub.34, D.sub.35 and D.sub.36 to the output terminal 34, respectively, and by their drains commonly to a power supply terminal 31. This circuit has two negative power supply terminals, namely a first negative power supply terminal 32 corresponding to 12 of FIG. 1 and another negative power supply terminal 35 to which load resistors R.sub.33 and R.sub.34 of the source-follower MESFETs Q.sub.33 and Q.sub.34 are commonly connected. The diodes D.sub.31 to D.sub.33 and D.sub.34 to D.sub.36 are for leveling down source follower outputs so as to meet the input levels.
Generally, normally-on a type MESFET has an advantage of providing a larger on-current than a normally-off type MESFET as shown in FIG. 4 and in the circuit of FIG. 3. By this large on-current, logic swing of the circuit is expanded thereby resulting in increasing of allowable range of deviation of the threshold voltage .DELTA.V.sub.T to be 0.5 to 1.0 V. However, this conventional latch of FIG. 3 has a shortcoming of a large operating current and the necessity of many diodes for level adjustments of outputs and further necessitates two power supplies. Therefore, its power consumption is very large such that 10 to 100 times more power consumption is used than for the conventional normally-off type MESFET latch.